Multiple power/performance points: All subsystems are able to operate at more than one power-performance level. Estimates indicate that this capability would result in a potential power savings that ranges from 20% to 60%.
Power islands: These independent subsystems are responsible for a meaningful fraction of the system power consumption (around 10%). Each subsystem operates at its own voltage levels and clock frequencies, thereby enabling dynamic power management. The power-reduction impacts are estimated to be in the range of 5% to 40%.
Thermal islands: These independent subsystems are responsible for a meaningful fraction of the system heat generation (around 10%). Each subsystem operates its own thermal level (with sensor and power-level control). Power-reduction ranges depend heavily on specific implementations.
Resource scheduler: This software and hardware structure handles CBPM techniques. System-level silicon-area penalties are estimated to be around 5%. Power-consumption-reduction estimates are heavily dependent on the specifics of each implementation. Technical literature cites extreme examples of a 3X improvement in battery life being achieved.
Sensors for environment context: These sensors monitor aspects like system and ambient temperature, ambient light, battery-charge levels, and user movement. Estimates indicate that this capability would result in a potential power savings of around 10%.
Fine-grain idleness control: These software and hardware structures enable the idleness control of granular system components. This control is invisible to the user. It might include, for example, drowsy caches and processor cores like ARM's ARM1176 IEM-enabled RISC core.
Although cost isn't included in this article's analysis, a smart system designer will select the optimal mix in order to achieve the best cost/battery-life combination for the intended cellular-phone device. By carefully selecting the basic elements that will be used in a design, the designer can keep cost within budget while implementing a wide range of energy-management techniques. The semiconductor components that are included in a cellular-phone design are responsible for a major share of the power that's dissipated. Aside from being developed with features that must support system-level energy-management techniques, these components must also be inherently low-power-consuming structures.

Most of the semiconductor devices that are used in systems like wireless cellular phones are fabricated in CMOS processes. The power that's dissipated by CMOS structures is composed of two factors: dynamic and static power dissipation. Dynamic power dissipation results from the active switching of the transistors' logic state. In contrast, static power dissipation occurs because of the current that leaks from the transistors while they're powered.

The main contributors to the dynamic power dissipation of CMOS structures are the applied voltage, operating frequency, and switching-structure capacitance. For static power dissipation, the main contributors are the applied voltage and the threshold voltage (Vt) of the used transistors. Of course, the silicon manufacturing process also has a huge influence on the overall power that is dissipated.